Honored ContributorFor some reason my projects stop compiling when the Analysis and Synthesis reach Elaborating Higher level entity. Even projects that had compiled perfectly in the past have failed to compile now because of this problem.
My professor and myself are stumped as to the cause of my dilema. if anyone can shed some light on this mystery I would appreciate any help.
Honored ContributorDid you solve this issue?
I have the same problem here. Quartus II 11.1 with a VHDL design. In every of my designs it hangs at the "elaborating...." between 9% and 18%. Demo designs in Verilog can be compiled, but I don't see any setting changes compared to my project(s).Honored Contributoryou could have something in your code that unrolls to a very large loop or generates a big bunch of logic that the Quartus synthesizer isn't able to process. It usually stops with an error, but I've seen it getting stuck in some cases too.
Honored ContributorIndeed, yesterday night I discovered that too.
Adjusted the code and now the problem is gone. Thanks! :cool:
