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Altera_Forum
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14 years ago

Stuck at elaborating higher level entity

For some reason my projects stop compiling when the Analysis and Synthesis reach Elaborating Higher level entity. Even projects that had compiled perfectly in the past have failed to compile now beca...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Did you solve this issue?

I have the same problem here.

Quartus II 11.1 with a VHDL design.

In every of my designs it hangs at the "elaborating...." between 9% and 18%.

Demo designs in Verilog can be compiled, but I don't see any setting changes compared to my project(s).