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Altera_Forum's avatar
Altera_Forum
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17 years ago

Stratix III M9K/M144K true-dual-port support 1/2 the max width.

Update:

ugh, sorry, never mind... found that it does specify that true-dual port cuts max width in half later in http://altera.com/literature/hb/stx3/stx3_siii51004.pdf

... missed it before.

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When compiling in Quartus II for Stratix III, I'm getting twice as many M9Ks (& M144Ks) as I expected.

You can see what I mean without even compiling. When I use the MegaWizard Plug-In Manager to create a "RAM: 2-PORT", I find that anytime true-dual-port is selected and the width is > 1/2 max width, that it requires 2x the number of M9Ks or M144Ks.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Because the routing in an FPGA is configurable, and therefore takes a lot of silicon, adding ports into a RAM is not an insignificant amount of the die. (Most people think of the number bits as the only important part, which is more true for an ASIC). So tricks like are done like using them all in single port mode and only half in dual-port is done(i.e. only have X many ports and use them as much as possible.)

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I observed the same behavior and wondered what was going on. Where exactly in the document that the OP linked is the explanation?

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    page 4-13:

    --- Quote Start ---

    The widest bit configuration of the M9K and M144K blocks in true dual-port mode is as follows:

    ■ 512 × 16-bit (×18-bit with parity) (M9K)

    ■ 4K × 32-bit (×36-bit with parity) (M144K)

    Wider configurations are unavailable because the number of output drivers is equivalent to the maximum bit width of the respective memory block. Because true dual-port RAM has outputs on two ports, its maximum width equals half of the total number of output drivers.

    --- Quote End ---

    Thanks for making me feel better about not being the only one to miss it the 1st time thru. :) -Brian