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GLT1's avatar
GLT1
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

Stratix 10 I/O count discrepancy

Hello,

I have a design with 371 I/O pins that I'm attempting to fit into a 1SG040HH3F35E3VG device.

According to the Intel documentation and the Pin Planner, this device should have 374 user I/O pins. I am assigning the pins to I/O banks using the pin planner, and the list of I/O banks shows that I still have 3 pins available (371 + 3 = 374), which is correct.

However, when I run the I/O Assignment analysis or fitter I get the following error message which indicates there are only 366 I/O pins available:

Error (179000): Design requires 371 user-specified I/O pins -- too many to fit in the 366 user I/O pin locations available in the selected device

Info (179001): Current design requires 371 user-specified I/O pins -- 371 normal user-specified I/O pins and 0 programming pins that have been constrained to use dual-purpose I/O pin locations

Info (179002): Targeted device has 366 I/O pin locations available for user I/O -- 332 general-purpose I/O pins and 34 dual-purpose I/O pins

Why is Quartus Prime Pro (v21.3) saying there are only 366 I/O pins available instead of the expected 374?

Thanks,

Terry

  • AminT_Intel's avatar
    AminT_Intel
    3 years ago

    Hello,

    These pins are unassigned so you can safely ignore it.

    Thank you

5 Replies

  • AminT_Intel's avatar
    AminT_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hello Terry,

    I am sorry that you are facing this issue. I am here to try to help you. So you mentioned that you are expecting 371 pins available but when you ran the I/O Assignment Analysis you received and error saying that there are 366 I/O pins available.

    May I know if you have checked again if you have used any of the available pins? It would also be helpful if you could send me a screenshot of the errros you have received.

    Thank you.

  • GLT1's avatar
    GLT1
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    Hello,

    Yes. I've tweaked the design a little bit since my original post and am now down to 369 pins, but the error message is the same. See the attached images for the list of I/O banks from the Pin Planner, which shows there are 5 available pins in the non-transceiver banks. Also, there is a screen shot of the error messages.

    Thank you,

    Terry

  • GLT1's avatar
    GLT1
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    I was able to reduce the IO count of my design, constrain all pins to I/O banks and eventually get everything to fit.

    The current design has 371 pins in use and 3 spares, for a total of 374 pins ... which is the expected pin count.

    I don't understand why the tools were reporting only 366 pins available before, but it is working now.

    Quartus Prime Pro is actually now reporting that I am using 389 pins, however this includes 18 "unassigned" pins that are showing up in the output pins report (see attached image).

    These pins are not part of my design and I don't know where they came from. Can these pins be safely ignored?

    Thanks,

    Terry

    • AminT_Intel's avatar
      AminT_Intel
      Icon for Regular Contributor rankRegular Contributor
      3 years ago

      Hello,

      These pins are unassigned so you can safely ignore it.

      Thank you

      • AminT_Intel's avatar
        AminT_Intel
        Icon for Regular Contributor rankRegular Contributor
        3 years ago

        I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.