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GLT1's avatar
GLT1
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

Stratix 10 I/O count discrepancy

Hello, I have a design with 371 I/O pins that I'm attempting to fit into a 1SG040HH3F35E3VG device. According to the Intel documentation and the Pin Planner, this device should have 374 user I/...
  • AminT_Intel's avatar
    AminT_Intel
    4 years ago

    Hello,

    These pins are unassigned so you can safely ignore it.

    Thank you

GLT1's avatar
GLT1
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

I was able to reduce the IO count of my design, constrain all pins to I/O banks and eventually get everything to fit.

The current design has 371 pins in use and 3 spares, for a total of 374 pins ... which is the expected pin count.

I don't understand why the tools were reporting only 366 pins available before, but it is working now.

Quartus Prime Pro is actually now reporting that I am using 389 pins, however this includes 18 "unassigned" pins that are showing up in the output pins report (see attached image).

These pins are not part of my design and I don't know where they came from. Can these pins be safely ignored?

Thanks,

Terry

AminT_Intel's avatar
AminT_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hello,

These pins are unassigned so you can safely ignore it.

Thank you

  • AminT_Intel's avatar
    AminT_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.