Stratix 10 Dual port ram with byte enable

Hi @aesq ,

You didn't say which of the available memory types you're referring to. I'm assuming you meant M20K block RAM.

The Stratix 10 M20K block RAM supports TDP operation in aspect ratios of either 1K deep X 20 bits wide or 2K deep X 10 bits wide. And multiple M20K block RAMs can be combined in various ways, depth-wise and width-wise, to construct larger memories.

You can physically construct your logical memory with byte enables by breaking it up width-wise into byte lanes. Implement the memory from multiple 8-bit wide lanes, where each lane is implemented using one (or more depending on depth) M20K block RAM, physically configured to use the 2K deep X 10 bit wide aspect ratio. And implement your byte enables by logically ORing them into the corresponding write enable of each lane.

Anyhow, this may even be a more detailed explanation than you need for your purpose, depends on what you're trying to accomplish. Ultimately, for most applications, you don't need to explicitly instantiate and configure M20K resources in your code. You'll be best off simply inferring the memory characteristics that you need in plain RTL, with the appropriate number of pipeline register stages, and then let Quartus map that inference efficiently to the the available physical resources. You should still go back and verify that Quartus implements it in an efficient manner as intended, but generally it should if you inferred your memory properly.

-Roee