ContributionsMost RecentMost LikesSolutionsRe: Fitter routing operation verbosity I will try the same option as I indicated in the other topic to solve the routing problem in the cyclone V: set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION OFF Re: Fitter can't fit a small design in Cyclone V SE that fits in a much smaller Cyclone IV device Hi, As I was facing a similar issue with my project, I took his example and played with the options, placement and so on. I found an option that makes the routing ok (I changed to my Cyclone V type). Intel should investigate why this option makes the routing failing. See picture showing the option, change it from ON to OFF. This was tested with Quartus 21.1.1 std. Re: Stratix 10 Dual port ram with byte enable What I do is that I provide a dual port RAM RTL code to Synplify and the generated verilog netlist is used by Quartus. Synplify says that dual port ram is not supported in Stratix 10, which is the case. Same RTL code also fails when synthesized in Quartus. Do you have any other RTL code proposal that Could be used and Working for Synplify and Quartus? I cannot copy my code or attach it, it is blocked by the company... Re: EThernet Blaster protocol At my side I use an Ethernet blaster II that works fine when connected to a Cyclone V FPGA. I can run the Quartus programmer/signal tap from either Linux or Windows. For this a Fix IP address is dedicated to the MAC address of the Ethernet blaster 2. To be noted that the Ethernet blaster 2 is only stable using a 100 Mpbs network setting and where the" fast port" switch ethernet option is turned off (otherwise the connection is being lost after few seconds). Re: Current module quartus_fit was unexpectedly terminated by signal 9 64 GB apparently, so twice more than what you have: https://www.intel.com/content/www/us/en/docs/programmable/683706/23-4/disk-space-and-memory-recommendations.html Stratix 10 Dual port ram with byte enable Hello, It is known that the Stratix 10 does not support true dual port ram with byte enable. But would it be possible to have a dual port ram with 2 different clocks, where one port uses the byte enable and the second port without the byte enable? Idea is to have one port using the functional part of the design which requires the byte enable, while the second port is used as a backdoor port to read or write the RAM content. And for this we do not need the byte enable on the second backdoor access port. Kind Regards, Alex. Re: Global clock control assignment for Arria10 Hi, I couldn't transfer the Intel login account, I created a new one based on another email. Have a nice day. Alex.