std_logic to std_logic_vector in port map

I am newbie in VHDL design and reading literature did not help ...

I created entity to sync signal(s) to clk. I would like to have it generic and use it for both single signals (n=1) and vectors (n>1). The entity is declared as:

entity sync2 is
    generic (
        n           : positive := 2      -- width
    );
    port (
        -- inputs
        d           : in  std_logic_vector (n-1 downto 0);
        clk         : in  std_logic;     -- clock
        reset       : in  std_logic;     -- asynchronous reset
        -- outputs
        q           : out std_logic_vector (n - 1 downto 0)
    );
end entity sync2;

It works perfectly for vectors but I do not know, how to connect std_logic signal to the input vector, which is in this case std_logic_vector(0 downto 0);

Or is it possible to overload the declaration so the d is std_logic?

signal sig1    : std_logic;
signal sig2    : std_logic;
-------------------------------------------------------------------------------
-- Instantiation of entity
-------------------------------------------------------------------------------
    sync : entity work.sync2
        generic map ( n => 1 )
        port map (
            d              => sig1,
            q              => sig2,
            reset          => reset,
            clk            => clk
        );