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Altera_Forum's avatar
Altera_Forum
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18 years ago

std_logic to std_logic_vector in port map

I am newbie in VHDL design and reading literature did not help ... I created entity to sync signal(s) to clk. I would like to have it generic and use it for both single signals (n=1) and vector...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hi,

If n is say 2 and you want just put a std logic signal into d you have to do something like

d => '0' & sig1,

which fills up the other spaces with zero.

If n = 3 it'll be

d => "00" & sig1,

notice the double quotation marks this time.

& is used for concatination in VHDL.

Cheers