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Altera_Forum's avatar
Altera_Forum
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18 years ago

std_logic to std_logic_vector in port map

I am newbie in VHDL design and reading literature did not help ... I created entity to sync signal(s) to clk. I would like to have it generic and use it for both single signals (n=1) and vector...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Yes, but what if n = 1. How do I code it? In meantime i found i can use following syntax: 

    sync : entity work.sync2
        generic map ( n => 2 )
        port map (
            d(0)          => sig1,
            q(0)           => sig2,
            reset          => reset,
            clk            => clk
        );