State machine fail to hold default value

Hi, all

Here's example of my state machine coding in verilog:

--- Quote Start ---

always @(posedge clkADC or posedge RST)

begin

if (RST)

state <= s0;

else

case (state)

s0: if (START) state <= s1; else state <= s0;

s1: ns <=s2;

s2: ns <=s3;

s3: ns <= s0;

endcase

end

always@(state, DataIn)

begin

case (state)

s1:begin

fifo_wreq <= 1;

Data <= DataIn;

end

s2:begin

Data <= DataIn;

end

s3:begin

Data <= DataIn;

fifo_wreq <= 1;

end

default:begin

Data <= 12'b000000000000;

fifo_wreq <= 0;

end

endcase

end

--- Quote End ---

fifo_wreq at s2 suppose to be default value, which is 0. However, I found out that it remain 1 at state machine s2. May I know any mistake i do so far?