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Honored Contributor

11 years ago

State machine fail to hold default value

Hi, all Here's example of my state machine coding in verilog: --- Quote Start --- always @(posedge clkADC or posedge RST) begin if (RST) state <=...

Honored Contributor

10 years ago

--- Quote Start ---

No, once you assign a value to a variable, it stays at that value until it is assigned again

Ensure all variables are assigned in all cases in non-clocked always blocks. They should preferably be assigned with non-blocking assignments..

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Variables in a non-clocked always block should be assigned with blocking assignments.

Clocked always blocks should use non-blocking assignments.