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Altera_Forum
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11 years ago

State machine fail to hold default value

Hi, all Here's example of my state machine coding in verilog: --- Quote Start --- always @(posedge clkADC or posedge RST) begin if (RST) state <=...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Hi, Tricky

Thanks for reply. For my understanding, if I didn't assign fifo_wreq to 0 in s2, suppose fifo_wreq value is followed by the default value as stated 0. Am I right?

May I know how to prevent the latch happen?