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Altera_Forum
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11 years ago

State machine fail to hold default value

Hi, all Here's example of my state machine coding in verilog: --- Quote Start --- always @(posedge clkADC or posedge RST) begin if (RST) state <=...
Altera_Forum's avatar
Altera_Forum
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11 years ago

You didnt assign it to 0 in s2. In the second always block, you need to assign all values in all states.

S1 will occur before s2, therefore fifo_wreq has already been set to 1 in the previous state. You created a latch (which is not a good thing) but letting it remember it's value between states.