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Altera_Forum's avatar
Altera_Forum
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11 years ago

State Machine - define an initial state

Hi, so I'm doing this activity and I have to make a controller, but it does not have a reset or any input. It have to start the moment I put power on the circuit. Here comes the problem, when I try to simulate (an example of my code is below) it starts on a different state (not the one i want). I know why it's wrong, I just don't know how to fix, how to tell - in VHDL - which one is my initial state.

example of my code:

(...)

architecture beh of FSM is

type states is (Initial_state , second_state , third_sate );

signal EA: states;

begin

process (clock, EA)

begin

if clock'event and clock = '1' then

Case EA is

when Initial_state =>

EA <= second_state;

when second_state =>

EA <= third_state;

when third_state =>

EA <= Initial_state;

end case;

(...)

Thank you!

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    in VHDL, any signal without an initial value will initialise to type'left

    So in this case, the EA signal will start with the "initial_state" value
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    for simulating i think you can define it when you create the signal i.e.

    signal EA : states := Initial_state;

    or

    signal EA : states := Second_state;

    depending where you want it to start
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    for simulating i think you can define it when you create the signal i.e.

    signal EA : states := Initial_state;

    or

    signal EA : states := Second_state;

    depending where you want it to start

    --- Quote End ---

    That should also affect the power up state of the state registers during synthesis - but it's just easiest to leave it to initialise to the left most defined value.