Forum Discussion
Altera_Forum
Honored Contributor
11 years ago --- Quote Start --- for simulating i think you can define it when you create the signal i.e. signal EA : states := Initial_state; or signal EA : states := Second_state; depending where you want it to start --- Quote End --- That should also affect the power up state of the state registers during synthesis - but it's just easiest to leave it to initialise to the left most defined value.