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Altera_Forum's avatar
Altera_Forum
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11 years ago

SPI Master/Slave Interface

Dear All,

I am trying to simulate the testbench of the master and slave SPI interfaces from the opencores.org website but I get the following error message:

error (10533): VHDL wait Statement error at spi_loopback_test.vhd(209): wait Statement must contain condition clause with until keyword

I am using Quartus for the VHDL files and Modelsim to view the testbench results. Also, I have set the "spi_loopback_testbench.vhd" file as the "Top-Level Entity".

I will appreciate it if anyone can help me figure out how to solve the error. Please find the files attached.

Thank you.

Kind regards,

Deadman

https://www.alteraforum.com/forum/attachment.php?attachmentid=9987 https://www.alteraforum.com/forum/attachment.php?attachmentid=9988 https://www.alteraforum.com/forum/attachment.php?attachmentid=9989 https://www.alteraforum.com/forum/attachment.php?attachmentid=9990 https://www.alteraforum.com/forum/attachment.php?attachmentid=9991

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Google the phrase "ModelSim Error (10533)" and I think you'll find some answers.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Google the phrase "ModelSim Error (10533)" and I think you'll find some answers.

    --- Quote End ---

    This is not an error in Modelsim, it is an error in Quartus.

    Deadman
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    You don't set the testbench as the top-level entity for Quartus to compile but the actual top-file you are going to simulate, in this case 'spi_loopback.vhd'.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    You don't set the testbench as the top-level entity for Quartus to compile but the actual top-file you are going to simulate, in this case 'spi_loopback.vhd'.

    --- Quote End ---

    I simulated the "spi_loopback.vhd" file and I get errors on the test bench as shown in the picture below. I am not sure why I am getting these errors.http://www.alteraforum.com/forum/attachment.php?attachmentid=10010&stc=1

    Deadman
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    You don't set the testbench as the top-level entity for Quartus to compile but the actual top-file you are going to simulate, in this case 'spi_loopback.vhd'.

    --- Quote End ---

    I simulated the "spi_loopback.vhd" file but I get errors as shown in the picture below. I am not sure why I am getting these errors.

    http://www.alteraforum.com/forum/attachment.php?attachmentid=10013&stc=1

    Deadman
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    You don't set the testbench as the top-level entity for Quartus to compile but the actual top-file you are going to simulate, in this case 'spi_loopback.vhd'.

    --- Quote End ---

    I simulated the "spi_loopback.vhd" file but I get the following errors as shown in the picture below. I am not sure why I am getting these errors.

    https://www.alteraforum.com/forum/attachment.php?attachmentid=10018

    Deadman
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Unfortunately the image to small to read, even with my 'computer glasses' :)

    Perhaps you can archive the project and either post the .qar here or send it to my private message box.

    Regards,

    Josy