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Altera_Forum's avatar
Altera_Forum
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11 years ago

SPI Master/Slave Interface

Dear All, I am trying to simulate the testbench of the master and slave SPI interfaces from the opencores.org website but I get the following error message: error (10533): VHDL wait Stat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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You don't set the testbench as the top-level entity for Quartus to compile but the actual top-file you are going to simulate, in this case 'spi_loopback.vhd'.

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I simulated the "spi_loopback.vhd" file and I get errors on the test bench as shown in the picture below. I am not sure why I am getting these errors.http://www.alteraforum.com/forum/attachment.php?attachmentid=10010&stc=1

Deadman