Forum Discussion

PJdesigns's avatar
PJdesigns
Icon for New Contributor rankNew Contributor
1 year ago
Solved

Simulation using Questa-Intel FPGA Edition with Quartus Prime Lite 23.1 and VWF file

Re-design of old schematic based design, (1994) and need to update to MAX V family CPLD. Trying to run the simulator on design using VWF file with an error generated, (see attached).
Hdl
  • RichardT_altera's avatar
    RichardT_altera
    1 year ago

    You can find it the "Simulation Waveform Editor " GUI.



    Regards,

    Richard Tan

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Thank you for acknowledging the solution provided. I'm pleased to know that your question has been addressed.


Now, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

The community users will be able to help you on your follow-up questions.


Thank you and have a great day!


Best Regards,

Richard Tan