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Honored Contributor
Honored ContributorSimulation problem with autogenerate verilog code
Hi,
I develope some CNN on openCL, compile with OpenCL FPGA compiler, and this CNN is work on the DevKit. But I want to simulation autogenerated verilog code which get after compilation. Simulation with Questa Sim. I added all files from project (which generated by OpenCL FPGA compiler), from BSP too. But QuestaSim get this error Module 'twentynm_fp_mac_encrypted' is not define. I can't find this module. Not in proj, not in BSP,not in Quartus. Can you tell me how can I solve this probem ?4 Replies
Altera_ForumJudging by "encrypted" in the module name I would expect that is an encrypted IP Core which can only be used in conjunction with Altera's tools.
- Altera_Forum
May be I can generate HDL-model of this module for simulation ?
- Altera_Forum
I am not really sure about that. I think you might have better luck asking in the "Quartus II and EDA Tools Discussion" section since the people there will likely have a better idea about such problems.
- Altera_Forum
Thank you, HRZ
