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Altera_Forum
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8 years ago

Simulation problem with autogenerate verilog code

Hi, I develope some CNN on openCL, compile with OpenCL FPGA compiler, and this CNN is work on the DevKit. But I want to simulation autogenerated verilog code which get after compilation. Simu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

I am not really sure about that. I think you might have better luck asking in the "Quartus II and EDA Tools Discussion" section since the people there will likely have a better idea about such problems.