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Altera_Forum
Honored Contributor
Honored ContributorSimulation problem with autogenerate verilog code
Hi, I develope some CNN on openCL, compile with OpenCL FPGA compiler, and this CNN is work on the DevKit. But I want to simulation autogenerated verilog code which get after compilation. Simu...
Altera_ForumHonored Contributor
Honored ContributorI am not really sure about that. I think you might have better luck asking in the "Quartus II and EDA Tools Discussion" section since the people there will likely have a better idea about such problems.
