Simulation fails when it goes into big design.

Ok guys, I have designed a small block that does some counting and put some signals to zero while its counting..

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY deadband  IS
PORT (
        CLKOUT: IN STD_LOGIC;
        T3PWM: IN STD_LOGIC;
        PWMB7: OUT STD_LOGIC;
        PWMB8: OUT STD_LOGIC
        );
END deadband;
ARCHITECTURE identifier OF deadband IS
signal EVBCONDB_reg : UNSIGNED (7 downto 0) := "00011000";
signal PWMB7_DB_reg : STD_LOGIC;
signal PWMB8_DB_reg : STD_LOGIC;
BEGIN
  PWMB7 <= PWMB7_DB_reg;
  PWMB8 <= PWMB8_DB_reg;
-- T3PWM Deadband
-----------------
    process(CLKOUT,EVBCONDB_reg)
    variable prev_T3PWM    : STD_LOGIC;
    variable counter_en    : STD_LOGIC;
    variable count : UNSIGNED (8 downto 0);
    variable multiplier : UNSIGNED (2 downto 0);
    begin
    
        case EVBCONDB_reg(2 downto 0) is        
            when "110" => multiplier := "101"; -- /1 divisor
            when "111" => multiplier := "101";    -- /2 divisor
            when others => multiplier := EVBCONDB_reg(2 downto 0);    -- /32 default
        end case;
        if(rising_edge(CLKOUT)) then
-- if we see a transition, start the clock and enable deadband
            if(prev_T3PWM /= T3PWM) then
                counter_en := '1';
                --count := EVBCONDB_reg(6 downto 3) * multiplier;
                count := "00000" & EVBCONDB_reg(6 downto 3);
                count := count sll TO_INTEGER(multiplier);
            end if;
                
-- if we've reached 0, stop counting and disable deadband
            if(count = "000000000") then
                counter_en := '0';
-- else decrement counter by one
            else
                count := count - 1;
            end if;
-- remember T3PWM for next time
            prev_T3PWM := T3PWM;
-- and output delayed PWM outputs
            PWMB7_DB_reg    <= T3PWM and not counter_en;
            PWMB8_DB_reg    <= not T3PWM and not counter_en;
        end if; -- if rising_edge(CLKOUT)
    end process;
        
END identifier;

When it is in its own project, the timing simulation would show that it's all good.

However, when I incorporate it into the big project, the timing simulation would fail, however the functional simulation shows that it does what its supposed to do.

Then I thought its a timing problem, but the compilation flow summary says all timing requirements have been met. So what's up?

Note: Within the failed timing simulation results, this thing doesn't stop counting and the counts are not normal, once in awhile it would jump to a number far away (not wraparound).

Thanks.