Simulation fails when it goes into big design.

What do you mean by "start the clock"?

Have a look at this document (http://www.altera.com/literature/wp/wp-01082-quartus-ii-metastability.pdf) from Altera that explains a few things about metastability. I think you should create a false path on your input signal in your timing requirements, so that Quartus doesn't have to try to meet any setup/hold requirements you don't need, and add a two registers chain between the input and your logic. Have a look at figure 3, and imagine that "Clock 2 domain" is your logic in the FPGA, and "clock 1 domain" is the signal source outside the FPGA.