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Altera_Forum's avatar
Altera_Forum
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15 years ago

Simulation fails when it goes into big design.

Ok guys, I have designed a small block that does some counting and put some signals to zero while its counting.. library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; u...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I've managed to build a synchronizer and have it verified by the RTL viewer. Now, how do I set the simulation to simulate that first flip flop to have a setup and hold time of 0 ns?

Why am I doing that? We'll thats the advice from one the threads I read about simulating these synchronizers.