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SMS
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7 years ago
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Simulating Soft LVDS Tx and Rx IP cores

I am trying to simulate the LVDS Tx and Rx IP cores, but when I run RTL simulation, Modelsim gives an error: Failed to open design unit file "C:/Users/Sarmad/Documents/Altera/LVDS_Test/LVDS_Rx.vo" ...
  • AnandRaj_S_Intel's avatar
    7 years ago

    ​Hi,

    Yes, you are correct I have used ALTLVDS IP core.

    I have also used Soft LVDS Intel FPGA IP.

    Steps:

    1. generated Soft LVDS Intel FPGA IP tx & rx individually
    2. Integrated it into top level HDL file.
    3. Generated a combined, version-independent simulation script file including both IP's using ip-setup-simulation command.Attached images
    4. Create a simple scrip to set top level HDL file and simulate.

    Example:

    set QSYS_SIMDIR C:/Users/anandr1x/Desktop/softlvdssim
    source mentor/msim_setup.tcl 
     
    #dev_com
    # Override the top-level name (so that elab is useful)
    set TOP_LEVEL_NAME softlvdssim 
    # Compile the standalone IP.
    com
    # Compile the user top-level vlog -sv ../../top.sv
    vlog -sv softlvdssim.v
    # Elaborate the design.
    elab

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Regards

    Anand