SMS
New Contributor
7 years agoSimulating Soft LVDS Tx and Rx IP cores
I am trying to simulate the LVDS Tx and Rx IP cores, but when I run RTL simulation, Modelsim gives an error: Failed to open design unit file "C:/Users/Sarmad/Documents/Altera/LVDS_Test/LVDS_Rx.vo" ...
- 7 years ago
Hi,
Yes, you are correct I have used ALTLVDS IP core.
I have also used Soft LVDS Intel FPGA IP.
Steps:
- generated Soft LVDS Intel FPGA IP tx & rx individually
- Integrated it into top level HDL file.
- Generated a combined, version-independent simulation script file including both IP's using ip-setup-simulation command.Attached images
- Create a simple scrip to set top level HDL file and simulate.
Example:
set QSYS_SIMDIR C:/Users/anandr1x/Desktop/softlvdssim source mentor/msim_setup.tcl #dev_com # Override the top-level name (so that elab is useful) set TOP_LEVEL_NAME softlvdssim # Compile the standalone IP. com # Compile the user top-level vlog -sv ../../top.sv vlog -sv softlvdssim.v # Elaborate the design. elabLet me know if this has helped resolve the issue you are facing or if you need any further assistance.
Regards
Anand