Contributorsimulate AN812
Dear Intel support and FPGA expert,
I am learning Arria 10 dev system. I compiled AN812 and load it successfully to the board. to get better understanding of the DDR4 and EMIF interface. I am creating a simulation environment based on AN812. AN812 was created for Quartus Pro 17. first I need to upgrade to Quartus 21.3. everything compile smoothly, but the top level module, which is top_system. failed to generated testbench. I copied a small section descript the errors.
Info: Starting: Create testbench Platform Designer system
Info: C:/FPGA/an812_orig/complete/top_system_tb/top_system.ipx
Info: qsys-generate C:\FPGA\an812_orig\complete\top_system.qsys --testbench=STANDARD --output-directory=C:\FPGA\an812_orig\complete --family="Arria 10" --part=10AX115S3F45I2SG
Info: Loading complete/top_system.qsys
Info: Reading input file
Info: Parameterizing module cpu_subsystem
Info: Parameterizing module emif_0
Info: Parameterizing module ext_clk
Info: Parameterizing module ext_reset
Info: Parameterizing module memory_tester_subsystem
Info: Building connections
Info: Parameterizing connections
Info: Validating
Info: Done reading input file
Info: qsys-generate succeeded.
Error: Error: Validation of the system failed
Error: There were errors creating the testbench system.
Info: Finished: Create testbench Platform Designer system.
What does this error means? I didn't see it generated any top_system_tb.v or anything like that.
so, I use Quartus-> processing-> start->start testbench template writer. created a top_level.vt.
and use platform designer opened emif_0 qsys. inside top_system_emif_0_tb, the Platform designer will create a mem_bfm_ip. I guess this is a generic DDR4 behavior model. can I instantiate this module in the AN812 top_level?
I did put this module in the top_system.vt, but after some struggle, I can compile and run the simulation. but the behavior is not as expected. I will post the result in another session.
Thank you for all the support,
David
top_system_emif_0_inst_mem_bfm_ip top_system_emif_0_inst_mem_bfm (
.sig_mem_ck (top_system_emif_0_inst_mem_mem_ck), // input, width = 1, conduit.mem_ck
.sig_mem_ck_n (top_system_emif_0_inst_mem_mem_ck_n), // input, width = 1, .mem_ck_n
.sig_mem_a (top_system_emif_0_inst_mem_mem_a), // input, width = 17, .mem_a
.sig_mem_act_n (top_system_emif_0_inst_mem_mem_act_n), // input, width = 1, .mem_act_n
.sig_mem_ba (top_system_emif_0_inst_mem_mem_ba), // input, width = 2, .mem_ba
.sig_mem_bg (top_system_emif_0_inst_mem_mem_bg), // input, width = 1, .mem_bg
.sig_mem_cke (top_system_emif_0_inst_mem_mem_cke), // input, width = 1, .mem_cke
.sig_mem_cs_n (top_system_emif_0_inst_mem_mem_cs_n), // input, width = 1, .mem_cs_n
.sig_mem_odt (top_system_emif_0_inst_mem_mem_odt), // input, width = 1, .mem_odt
.sig_mem_reset_n (top_system_emif_0_inst_mem_mem_reset_n), // input, width = 1, .mem_reset_n
.sig_mem_par (top_system_emif_0_inst_mem_mem_par), // input, width = 1, .mem_par
.sig_mem_alert_n (top_system_emif_0_inst_mem_bfm_conduit_mem_alert_n), // output, width = 1, .mem_alert_n
.sig_mem_dqs (top_system_emif_0_inst_mem_mem_dqs), // inout, width = 4, .mem_dqs
.sig_mem_dqs_n (top_system_emif_0_inst_mem_mem_dqs_n), // inout, width = 4, .mem_dqs_n
.sig_mem_dq (top_system_emif_0_inst_mem_mem_dq), // inout, width = 32, .mem_dq
.sig_mem_dbi_n (top_system_emif_0_inst_mem_mem_dbi_n) // inout, width = 4, .mem_dbi_n
);
Hi David,
I think the mem_bfm should be the Intel BFM.
I'm not usually use the AN812 design to test the DDR4 and EMIF interface.
The EMIF IP can generate the example design to simulate and test the IP itself.
You can refer to Arria 10 EMIF Design Example User Guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20118.pdf
By simulating the example design, you can see all EMIF signals interaction from the memory initialization ,calibration flow and user accesses.
I'm not sure if this something that you trying to get but I'm sure this can give you a good understanding on how the DDR4 and EMIF interface simply work.
Thanks,
Adzim
