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dsun01's avatar
dsun01
Icon for Contributor rankContributor
4 years ago
Solved

simulate AN812

Dear Intel support and FPGA expert, I am learning Arria 10 dev system. I compiled AN812 and load it successfully to the board. to get better understanding of the DDR4 and EMIF interface. I am crea...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    4 years ago

    Hi David,


    I think the mem_bfm should be the Intel BFM.

    I'm not usually use the AN812 design to test the DDR4 and EMIF interface.

    The EMIF IP can generate the example design to simulate and test the IP itself.

    You can refer to Arria 10 EMIF Design Example User Guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20118.pdf


    By simulating the example design, you can see all EMIF signals interaction from the memory initialization ,calibration flow and user accesses.

    I'm not sure if this something that you trying to get but I'm sure this can give you a good understanding on how the DDR4 and EMIF interface simply work.


    Thanks,

    Adzim


AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi David,


I think that are part of the transaction process of the DDR operation.

As you can see that they are trying to perform the read and write operation at the moment.


I don't think you can turn off or hide this particular message/warning.

It's should be contained an important info whenever the memory performs the wrong transaction.

But I think your design is doing good and maybe you can ignore that message.


Thanks,

Adzim


dsun01's avatar
dsun01
Icon for Contributor rankContributor
4 years ago

Thank you Adzim.