dsun01
Contributor
4 years agosimulate AN812
Dear Intel support and FPGA expert,
I am learning Arria 10 dev system. I compiled AN812 and load it successfully to the board. to get better understanding of the DDR4 and EMIF interface. I am crea...
- 4 years ago
Hi David,
I think the mem_bfm should be the Intel BFM.
I'm not usually use the AN812 design to test the DDR4 and EMIF interface.
The EMIF IP can generate the example design to simulate and test the IP itself.
You can refer to Arria 10 EMIF Design Example User Guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20118.pdf
By simulating the example design, you can see all EMIF signals interaction from the memory initialization ,calibration flow and user accesses.
I'm not sure if this something that you trying to get but I'm sure this can give you a good understanding on how the DDR4 and EMIF interface simply work.
Thanks,
Adzim