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Altera_Forum's avatar
Altera_Forum
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13 years ago

Signed adder and subtractor

Hi, I don't know if this is the ideal forum to ask, but I hope someone could help me!

I need to make a simple adder and a subtractor, signed (2's complement), with 9-bits in, 10-bits out, really any bits, I'll have to make several different bits adder/subtractor. It can be 2 different entities, one for adder and one for subtractor.

I'm having a problem cause of the overflow, sometimes i have my answer in 8-bits and sometimes in 9-bits.. And I need my answer ALWAYS with 9-bit.

Its a little hard to explain, but I guess you guys that are used to programming knows what i'm talking...if not, please respond and I'll send some examples.

Oh..I'm using VHDL.

Really Thanks!!!

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    9 bit input, 10 bit output 

    use ieee.numeric_std package.all;
...
signal a: signed (8 downto 0);
signal b: signed (8 downto 0);
signal c: signed (9 downto 0);
...
c <= to_signed(to_integer(a), 10) + to_signed(to_integer(b), 10);
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    rbuggalho,

    I can't implement it now, but thanks for the code.

    I even made an overflow detection algorithm before thing in convert to integer and then again to signed.

    I'll try it later. Thanks again!
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    An alternative VHDL implementation with less typing: 

    
c <= resize(a, 10) + resize(b, 10);

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    dwh@ovro.caltech.edu,

    Thank you too!!

    I made both codes, but I can't compile either.

    I guess I need to convert from std_logic_vector to that signed signal (i've never used that before).

    Here's my code: 

    
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity adder8 is
    Port (	
			a: IN STD_LOGIC_VECTOR(8 DOWNTO 0); 
			b: IN STD_LOGIC_VECTOR(8 DOWNTO 0);
			c: OUT STD_LOGIC_VECTOR(9 DOWNTO 0)	  
		  );
end adder8;
architecture behaviour of adder8 is
signal ta: signed (8 downto 0);
signal tb: signed (8 downto 0);
signal tc: signed (9 downto 0);
begin
tc <= resize(ta, 10) + resize(tb, 10); //OR tc <= to_signed(to_integer(ta), 10) + to_signed(to_integer(tb), 10);
END behaviour;

    I need to atribute ta<=a, tb<=b and c<=tc

    Thanks!!
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    I made both codes, but I can't compile either.

    I guess I need to convert from std_logic_vector to that signed signal (i've never used that before).

    --- Quote End ---

    std_logic_vector is just a vector of bits. You need to convert to unsigned or signed depending on what you want those bits to mean. Eg, 

    
c <= std_logic_vector( resize(signed(a),10) + resize(signed(b),10) );

    where signed(a) and signed(b) convert the std_logic_vector a and b inputs to signed, and then resize makes them bigger, the add returns signed, so that result is converted back to std_logic_vector before being assigned to the output c.

    Cheers,

    Dave