Signed adder and subtractor

dwh@ovro.caltech.edu,

Thank you too!!

I made both codes, but I can't compile either.

I guess I need to convert from std_logic_vector to that signed signal (i've never used that before).

Here's my code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity adder8 is
    Port (	
			a: IN STD_LOGIC_VECTOR(8 DOWNTO 0); 
			b: IN STD_LOGIC_VECTOR(8 DOWNTO 0);
			c: OUT STD_LOGIC_VECTOR(9 DOWNTO 0)	  
		  );
end adder8;
architecture behaviour of adder8 is
signal ta: signed (8 downto 0);
signal tb: signed (8 downto 0);
signal tc: signed (9 downto 0);
begin
tc <= resize(ta, 10) + resize(tb, 10); //OR tc <= to_signed(to_integer(ta), 10) + to_signed(to_integer(tb), 10);
END behaviour;

I need to atribute ta<=a, tb<=b and c<=tc

Thanks!!