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Altera_Forum's avatar
Altera_Forum
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13 years ago

Signed adder and subtractor

Hi, I don't know if this is the ideal forum to ask, but I hope someone could help me! I need to make a simple adder and a subtractor, signed (2's complement), with 9-bits in, 10-bits out, reall...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

An alternative VHDL implementation with less typing: 


c <= resize(a, 10) + resize(b, 10);

Cheers,

Dave