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I made both codes, but I can't compile either.
I guess I need to convert from std_logic_vector to that signed signal (i've never used that before).
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std_logic_vector is just a vector of bits. You need to convert to unsigned or signed depending on what you want those bits to mean. Eg,
c <= std_logic_vector( resize(signed(a),10) + resize(signed(b),10) );
where signed(a) and signed(b) convert the std_logic_vector a and b inputs to signed, and then resize makes them bigger, the add returns signed, so that result is converted back to std_logic_vector before being assigned to the output c.
Cheers,
Dave
Honored Contributor
