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Altera_Forum's avatar
Altera_Forum
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8 years ago

SignalTAP v16+ and Clock Enable signal problem

I found a nasty problem with SignalTAP on Quartus v16 and up.

I've used Quartus v13.1 before and i often used Storage Qualifier signal as a clock enable. I've used "input port" option and clock enable signal to reduce the sample collection rate. It worked fine.

After i've moved to v16 (and then 16.1, 17.0) i found that storage qualifier doesn't work anymore. It either ignored or even work unpredictable at all.

So, is it know bug in SignalTAP on v16+ or Clock enable now accomplished by other way? Then how?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    I haven't heard of any changes with this or seen any issues with it. What exactly happens?

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    As i've wrote - Storage Qualifier is ignored in v16+. I see SignalTAP is collecting samples at full clock rate.

    I didn't try 14.0-15.x - so i don't know if this problem has been introduced earlier.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    What changes or anything have you done to the project as you've moved up in versions? Have you been updating IP and recompiling or are you using a version-compatible database? The feature works so it must be something in your project that has changed or not been updated that is preventing it from working for you.

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    It happens in all my projects, including new projects created in v16.