china_cn
New Contributor
3 years agoSignaltap:waiting for clock
I instantiated 4 Jesd204b IP cores in the program and generated link_clk with IOPLL. When I use link_clk as a sampling signal for signaltap, signaltap shows the waiting clock. And you can see an error message on the system message:
Data integrity error is detected during jtag communication. the signal tap result is not trustworthy.
I don't know why, can you answer that question for me.
Thank you.
Probably missing or incorrect timing constraints for the JTAG signals.
Can you check that these signals are correctly constrained?
https://www.intel.com/content/www/us/en/support/programmable/articles/000086649.html