Forum Discussion

china_cn's avatar
china_cn
Icon for New Contributor rankNew Contributor
4 years ago
Solved

Signaltap：waiting for clock

I instantiated 4 Jesd204b IP cores in the program and generated link_clk with IOPLL. When I use link_clk as a sampling signal for signaltap, signaltap shows the waiting clock. And you can see an erro...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
4 years ago

Error (12852): Data integrity error is detected during JTAG communication. The Signal Tap result is not trustworthy. Please check the JTAG chain.

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#msgs/msgs/echi_tdo_capture_integrity_err.htm

CAUSE: Signal Tap calculated CRC values of the data shifted out of the device once in the device at the source and once in the software as received by computer. The two CRC values don't match. The bits are corrupted during communication. The most likely cause is the signal integrity issue with JTAG chain.


This message is a clear indication that the physical JTAG chain is not properly designed that data communication cannot carried out. This is not a Quartus SW error. You will have to debug your board.


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.


  • china_cn's avatar
    china_cn
    Icon for New Contributor rankNew Contributor
    4 years ago

    I'm using the Intel-ARRIA 10-GX FPGA Development Kit, which doesn't look like it's a problem for the development board. For JTAG signal constraints, I only constrain the altera_reserved_tck to 33MHz and set it to an asynchronous clock, is it possible that there is a problem with timing constraints?
    Thank you