Forum Discussion
china_cn
New Contributor
New ContributorSignaltap：waiting for clock
I instantiated 4 Jesd204b IP cores in the program and generated link_clk with IOPLL. When I use link_clk as a sampling signal for signaltap, signaltap shows the waiting clock. And you can see an erro...
Probably missing or incorrect timing constraints for the JTAG signals.
Can you check that these signals are correctly constrained?
https://www.intel.com/content/www/us/en/support/programmable/articles/000086649.html
RichardT_altera
Super Contributor
Super ContributorBased on the KDB, does not seem to be a problem with applying a 33-MHz clock constraint to this altera_reserved_tck pin.
https://www.intel.com/content/www/us/en/support/programmable/articles/000080925.html
