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china_cn's avatar
china_cn
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Signaltap：waiting for clock

I instantiated 4 Jesd204b IP cores in the program and generated link_clk with IOPLL. When I use link_clk as a sampling signal for signaltap, signaltap shows the waiting clock. And you can see an erro...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Great to see that you able to find a solution to move forward! Probably you might need to further debug the problematic USB Blaster to know what goes wrong.

Since you have a solution, do you need further help in regards to this case?


Regards,

Richard