Forum Discussion

Hamza_52's avatar
Hamza_52
Icon for New Contributor rankNew Contributor
3 years ago

Signal Tap Logic Analyzer II Trigger Condition

Hi i am working with DE1-SoC Cyclone V SoC FPGA Board and i am using quartus Prime Lite Edition. I am trying to use Signal Tap Logic Analyzer II but somehow i am not able to configure it correctly my...
Platform
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago
I don’t understand. You can make the buffer store more samples or you could use storage qualification to only capture relevant samples and drop samples you don’t care about.
Hamza_52's avatar
Hamza_52
Icon for New Contributor rankNew Contributor
3 years ago

ok thanks for clearing my doubts. I will get back to you if i have any more queries.