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Hamza_52's avatar
Hamza_52
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3 years ago

Signal Tap Logic Analyzer II Trigger Condition

Hi i am working with DE1-SoC Cyclone V SoC FPGA Board and i am using quartus Prime Lite Edition. I am trying to use Signal Tap Logic Analyzer II but somehow i am not able to configure it correctly my...
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Hamza_52's avatar
Hamza_52
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3 years ago

I mean i am just trying to understand that how it is working as i cant always make sure that the program i am running will be complete in 64 samples or it will take more than that so isnt there any way to set up such a configuration which works as per my design requirements

sstrell's avatar
sstrell
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3 years ago
I don’t understand. You can make the buffer store more samples or you could use storage qualification to only capture relevant samples and drop samples you don’t care about.
  • Hamza_52's avatar
    Hamza_52
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    3 years ago

    ok thanks for clearing my doubts. I will get back to you if i have any more queries.