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Hamza_52
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3 years ago

Signal Tap Logic Analyzer II Trigger Condition

Hi i am working with DE1-SoC Cyclone V SoC FPGA Board and i am using quartus Prime Lite Edition. I am trying to use Signal Tap Logic Analyzer II but somehow i am not able to configure it correctly my...
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Hamza_52
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3 years ago

Yes regarding the clock you are right. I was also thinking the same that may be my buffer is getting overwrite with 50 Mhz clock thats why i am only able to see one sample.

But disabling the trigger in so how the data acquisition will stop as i dont want any extra samples

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Hamza_52
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3 years ago

As the reason i am testing trigger in because i want to run a C program on one of my design which have to stop after a particular condition is match or if all the lines of the code is executed. I dont want to stop sampling before that and i also dont want samples after that