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Hamza_52
New Contributor
New ContributorSignal Tap Logic Analyzer II Trigger Condition
Hi i am working with DE1-SoC Cyclone V SoC FPGA Board and i am using quartus Prime Lite Edition. I am trying to use Signal Tap Logic Analyzer II but somehow i am not able to configure it correctly my...
sstrell
Super Contributor
Super ContributorSo what are you expecting to see?
You have stop~0 set as a trigger in (like trigger condition 0). You don't show what you have set up for your main trigger condition from the Signal Tap node list.
Hamza_52New Contributor
New ContributorMy logic is i have implemented a simple counter which count from zero and count till 15. Once it reach 15 it enable the stop bit which should act a trigger to stop my acquisition. As the FPGA clock is of 50MHZ so to slow down the count i have used clock divider which generate a clock of 1 Hz and my counter is updating on every posedge of the 1 Hz clock. I am trying to see all the values of my counter on Signal Tap which i am unable to see.
