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Hamza_52's avatar
Hamza_52
Icon for New Contributor rankNew Contributor
3 years ago

Signal Tap Logic Analyzer II Trigger Condition

Hi i am working with DE1-SoC Cyclone V SoC FPGA Board and i am using quartus Prime Lite Edition. I am trying to use Signal Tap Logic Analyzer II but somehow i am not able to configure it correctly my...
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ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,


Check this https://www.intel.com/content/www/us/en/docs/programmable/683819/22-4/continuous-mode-and-a-storage-qualifier.html

Make sure you're using non-segmented buffer in continuous mode instead of non-segmented buffer using a storage qualifier and segmented buffer. In the continuous data capture, Trig1 occurs several times in the data buffer before the Signal Tap logic analyzer trigger activates. The buffer must be full before the logic analyzer evaluates any trigger condition.


Thanks,

Best Regards,

Sheng