Forum Discussion
Hamza_52
New Contributor
New ContributorSignal Tap Logic Analyzer II Trigger Condition
Hi i am working with DE1-SoC Cyclone V SoC FPGA Board and i am using quartus Prime Lite Edition. I am trying to use Signal Tap Logic Analyzer II but somehow i am not able to configure it correctly my...
sstrell
Super Contributor
Super ContributorWhat do you have the trigger position in the .stp file set to? If you want to see more captured data from before the trigger occurs (to the right of the trigger in the waveform view), set it to the post-trigger position.
However, none of the 3 trigger position options would only show a single value unless either your signals are not toggling around the time of the trigger or you've set the size of the buffer incorrectly (only 1 sample perhaps?).
Also, of course, your sampling clock has to toggle so data gets captured at each rising edge.
Hamza_52Hi,
I have attached the snap of all the configuration set in my stp file. I have also tried all 3 different position but non of them work.
