Forum Discussion
New ContributorSignal tap hdl instantiation
I can submit a feature request to the tool specialists to see if this functionality can be implemented for the HDL flow. However, whether the request is accepted will depend on the business justification.
By the way, which Quartus edition are you using—Pro or Standard?
If you're using the Standard Edition, the chances of this feature being supported are quite low, as most enhancements are prioritized for the Pro Edition.
Regards,
Richard Tan
Super ContributorThank you sstrell for answering.
Unfortunately, with HDL instantiation of Signal Tap, you cannot directly create a unified trigger/data bus that also serves as a storage qualifier in the same flexible way as the GUI-generated .stp file. The HDL-instantiated IP requires explicit port assignments for data, trigger, and qualifier, and does not support bus aliasing or unified port mapping in the .stp file as the GUI does.
The HDL flow is less flexible for bus aliasing and unified port mapping compared to the GUI.
If you want a unified bus, you must create it in your RTL (e.g., concatenate data and trigger signals into one bus and connect that to both the data and trigger ports, or use the same signal for multiple ports). For the storage qualifier, you must explicitly connect the qualifier port to the desired signal in your RTL; you cannot assign it to a bus in the .stp file after generation.
Consider using the GUI flow if you need advanced aliasing or unified bus mapping.
Regards,
Richard
BrickmanThank you Richard
I have used the same bus in my RTL for data and trigger, but than I still have to alias them separately in the stp, even worse, I will need to change my RTL for every qualifier change.
At this point I reverted to the GUI flow.
Is there a plan to make the instantiation flow usable in future versions? as a user (who is not involved in the development) This looks like a simple GUI improving task, since the functionality is already in the GUI flow.
Ron
