Signal Tap does not see differential signal REFCLK

Let me know if there is any update from previous reply.

What are you using for your sampling clock? It would have to be faster than 322 MHz to accurately capture all 3 signals and I don't think Signal Tap supports a sampling clock that fast.

Hi, sstrell

Thank you for reply.

Perhaps I didn't explain the meaning of the question in sufficient detail.
As a sample clock, I use 100 MHz. The tap signal works at this frequency without question.
Additionally, I feed 2 frequencies (125 and 322 MHz) to the outer pins of the FPGA, which is higher than the clock sample of 100 MHz.
To make sure that the frequency data gets to the subsequent FPGA logic, I pass these frequencies through a divider counter with a divide factor of 120.
Accordingly, at the outputs of the dividers, I expect 125 MHz / 120 ~ 1 MHz and 322 MHz / 120 ~ 2.7 MHz. With both of these frequencies, the tap signal should cope without question.
The essence of my problem is that I see two input frequencies at the outputs of the external generator and on the pins of the FPGA, but I do not see them inside the FPGA using the Singal tap.
I'm not trying to see signals with a frequency of 322 MHz using a 100 MHz sample clock))
This is a debug circuit to confirm of receiving of input frequencies.
I also tried to pass the input frequencies through the PLL without frequency conversion as 1: 1, but with the subsequent division on the counter to lower it, but I also did not see the output frequency.

I apologize than the problem with FPGA pins configuration, but I am not sure.

Br, Dmitry

So you're trying to tap signals operating at about 1 MHz and about 2.7 MHz? Then you have the opposite problem of what I mentioned. The signals are so slow that they don't appear in the time seen in the capture buffer. What is your trigger condition? If you trigger on these divided signals themselves, you should be able to see them.

May I know if there is any update from previous reply?

Hi all who helped to me in this problem.

I will share the results that I found. Perhaps this will be useful to someone.

After first compilation the default FPGA project from GIT I see inconsistency between Pin Planner and Assignments from one side and results in Input Pins (Fitter report) on another side. You can see all that in attachments.
I think this result obviously do not allow to work the project in right manner.

It seems to me that this behavior is due to the fact that by default Quartus for signals of the LVDS type automatically creates a pair with the addition of "(n)" to the end of the name of the second signal. But by default, a pair of signals with the names "..._P" and "...N" is created in the project.
Unfortunately, Quartus' work with assignments is not a strong point. Changing assignments creates "garbage from old values" in assignment files, which have to be deleted manually (dancing with a tambourine).
After some effort, I cleaned out the assignment history and brought project into the desired state (After correction.jpg).
But this activity do not move me to desired result. (((
Faced with the need to manually intervene in editing the assignments, I'm not sure that I corrected the situation in full.

I decide to go by another way and stop the work with this FPGA project.

Thanks again everyone for the help.

Br, Dmitry.