Signal Tap does not see differential signal REFCLK

Hi all who helped to me in this problem.

I will share the results that I found. Perhaps this will be useful to someone.

After first compilation the default FPGA project from GIT I see inconsistency between Pin Planner and Assignments from one side and results in Input Pins (Fitter report) on another side. You can see all that in attachments.
I think this result obviously do not allow to work the project in right manner.

It seems to me that this behavior is due to the fact that by default Quartus for signals of the LVDS type automatically creates a pair with the addition of "(n)" to the end of the name of the second signal. But by default, a pair of signals with the names "..._P" and "...N" is created in the project.
Unfortunately, Quartus' work with assignments is not a strong point. Changing assignments creates "garbage from old values" in assignment files, which have to be deleted manually (dancing with a tambourine).
After some effort, I cleaned out the assignment history and brought project into the desired state (After correction.jpg).
But this activity do not move me to desired result. (((
Faced with the need to manually intervene in editing the assignments, I'm not sure that I corrected the situation in full.

I decide to go by another way and stop the work with this FPGA project.

Thanks again everyone for the help.

Br, Dmitry.