Signal Tap does not see differential signal REFCLK

Hi, sstrell

Thank you for reply.

Perhaps I didn't explain the meaning of the question in sufficient detail.
As a sample clock, I use 100 MHz. The tap signal works at this frequency without question.
Additionally, I feed 2 frequencies (125 and 322 MHz) to the outer pins of the FPGA, which is higher than the clock sample of 100 MHz.
To make sure that the frequency data gets to the subsequent FPGA logic, I pass these frequencies through a divider counter with a divide factor of 120.
Accordingly, at the outputs of the dividers, I expect 125 MHz / 120 ~ 1 MHz and 322 MHz / 120 ~ 2.7 MHz. With both of these frequencies, the tap signal should cope without question.
The essence of my problem is that I see two input frequencies at the outputs of the external generator and on the pins of the FPGA, but I do not see them inside the FPGA using the Singal tap.
I'm not trying to see signals with a frequency of 322 MHz using a 100 MHz sample clock))
This is a debug circuit to confirm of receiving of input frequencies.
I also tried to pass the input frequencies through the PLL without frequency conversion as 1: 1, but with the subsequent division on the counter to lower it, but I also did not see the output frequency.

I apologize than the problem with FPGA pins configuration, but I am not sure.

Br, Dmitry