Signal not assigned in init state

Hello,

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity buttonToKey is port(
    clk_50 : in std_logic;
    button : in std_logic_vector(5 downto 1);
    key: out std_logic_vector(31 downto 0)
);
end buttonToKey;
architecture behavior of buttonToKey is
    type state_type is ( init, evaluate, assign );
    signal state : state_type     := init;
    
    type my_array_type is array (0 to 3) of std_logic_vector(7 downto 0);
    signal key_int : my_array_type;
    signal index : integer := 0;
    
    signal count : unsigned( 18 downto 0 ) := ( others => '0' );
    
begin
    process( clk_50 )
    begin
        if rising_edge( clk_50 ) then
            if state = init AND count = 100 then                                                -- init and assign default char
                state <= assign;
                key_int( 3 ) <= x"61";                                         -- ASCII 'a'
                key_int( 2 ) <= x"61"; 
                key_int( 1 ) <= x"61";
                key_int( 0 ) <= x"61";
                count <= ( others => '0' );
                
            elsif state = evaluate then                                    -- check which button is pressed
                if button = "10000" then                                    -- button 5: increment ASCII character 
                    state <= assign;
                    count <= ( others => '0' );
                    if unsigned( key_int( index ) ) = x"7A" then        -- run circular between ASCII char 'a' and 'z'
                        key_int( index ) <= x"61";
                    else
                        key_int( index ) <= key_int( index ) + 1;
                    end if;
                elsif button = "00001" then                                -- button 1: move to next position (start with 1)
                    state <= evaluate;
                    if index = 3 then
                        index <= 0;                                                -- overflow protection
                    else
                        index <= index + 1;
                    end if;
                else
                    state <= evaluate;
                end if;
                
            elsif state = assign AND count = 100 then                                        --  assign any changed keys to output                                             
                count <= ( others => '0' );
                state <= evaluate;
                key <= key_int( 3 ) & key_int( 2 ) & key_int( 1 ) & key_int( 0 );
            else
                count <= count + 1;
            end if;
        end if;
    end process;
end behavior;

BEGIN                                                        
        -- code that executes only once       
    button <= "00000";
    wait for 80 ns;
    
    button <= "00000";
    wait for 80 ns;
    
    button <= "00000";
    wait for 80 ns;
    
    button <= "00000";
    wait for 80 ns;
    
WAIT;                                                       
END PROCESS init;                                           
always : PROCESS                                              
-- optional sensitivity list                                  
-- (        )                                                 
-- variable declarations                                      
BEGIN                                                         
        -- code executes for every event on sensitivity list  
WAIT;                                                        
END PROCESS always;    
-- clock generation process
process
begin
  clk_50 <= '1';
  wait for 10 ns;
  clk_50 <= '0';
  wait for 10 ns;
end process;       
                                                      
END buttonToKey_arch;