Signal not assigned in init state

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Without the testbench, we cannot see whats going wrong.

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Hello Tricky,

that is the actual test bench that is in use at the moment. It should start the state machine, go into theinit state with the 101st rising edge and assign key_int( 3..1 ) <= x"61"; . Then it should go to assign state after another 101 rising edges to combine the key_int(3..1) into the output key. The problem I am seeing is that key is always 0. So either it does not go into the init state, or it does not assign key_int or it never reaches the assign state. And I have trouble determining whether it is my code, something Quartus II specific or something completely different.

The reason why I wrote that "I took most of the code out" is that I reduced the test bench to what you see here to find the error. The test bench is pretty dumb at the moment, but should do a very simple thing..but it is not doing it.

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I also note you're using buttons in the design. Have you properly synchronised and debounced them?

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Yes, those are debounced in a separate module that feeds this buttontokey module. But this should not matter for the test bench, does it?

Thanks.

ninja edit: changed wording